1. Field of the Invention
The present invention generally relates to the field of fabricating semiconductor devices, and more particularly to a method for forming interconnection structures in the semiconductor devices.
2. The Related Art
Semiconductor devices are generally manufactured or fabricated on semiconductor material such as wafers by using a number of processing steps. The wafers may undergo multiple masking, etching and deposition processing steps to form electronic circuitry of the semiconductor devices. With high integration of the semiconductor devices, metal interconnection structures have developed rapidly in the field of fabricating semiconductor devices. The multiple masking and etching processes can be used to form recessed areas in the wafer, such as trenches, vias, and the like. The deposition process can be used to deposit a metal layer onto both the recessed areas and non-recessed areas of the wafer. After deposition, the metal layer on the non-recessed areas of the wafer is removed and the metal left in the recessed areas of the wafer form the interconnection structures. Particularly, the metal layer is deposited on a dielectric layer formed on the wafer, so in order to prevent the diffusion or leaching of the metal layer into the dielectric layer, a barrier layer is deposited on the dielectric layer before depositing the metal layer and the metal layer is then deposited on the barrier layer.
Conventional methods including, for example, chemical mechanical polishing (CMP) are adopted to remove the metal layer and the barrier layer on the non-recessed areas of the wafer. The CMP method is widely used in the semiconductor industry to polish and planarize the metal layer on the non-recessed areas of the wafer to form the interconnection structures. In a CMP process, the wafer is positioned on a CMP pad located on a platen. A force is then applied to press the wafer against the CMP pad. The CMP pad and the wafer are moved against and relative to one another while applying the force to polish and planarize the metal layer. A polishing solution, often referred to as polishing slurry, is dispensed on the CMP pad to facilitate the polishing. However, the CMP method has several deleterious effects on the semiconductor structure formed on the wafer because of the involved relatively strong mechanical force applied on the metal layer and the barrier layer in the CMP process.
Another method for removing the metal layer deposited on the non-recessed areas of the wafer is electropolishing. The electropolishing method can remove the metal layer with high uniformity and have high selectivity to the barrier layer. It is a mechanical stress free process. However, during the electropolishing process, in order to remove all the metal layer on the non-recessed areas of the wafer, over polish is conducted. But it is found that at the areas, such as field area, wide space area between two adjacent metal lines, and space area at two sides of an isolated metal line, because there is no metal on the non-recessed areas and the barrier layer is exposed after the metal layer is removed at the over polishing stage, the current is conducted through the barrier layer. Then the surface of the barrier layer will be oxidized to form an oxidization film on the top surface of those areas. Or in other words, the oxidization film is thicker at the areas having lower interconnection structure density than at the areas having higher interconnection structure density. Since the metal layer, such as copper, has much lower resistance, the current will mostly go through the metal layer instead of going through the barrier layer. The oxidization film prevents the barrier layer being removed in the barrier layer removal step, and the barrier layer can not be uniformly removed, causing the semiconductor device failure.